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MC100LVEL16 3.3V ECL Differential Receiver
Description
The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL16 is ideally suited for interfacing with high frequency sources at 3.3 V supplies. Under open input conditions, the Q input will be pulled down to VEE and the Q input will be biased to VCC/2. This condition will force the Q output low. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features
http://onsemi.com MARKING DIAGRAMS*
8 1 SOIC-8 D SUFFIX CASE 751 8 1 TSSOP-8 DT SUFFIX CASE 948R 8 KVL16 ALYW G 1
8 KV16 ALYWG G
* * * *
1 DFN8 MN SUFFIX CASE 506AA A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
December, 2006 - Rev. 5
1
Publication Order Number: MC100LVEL16/D
4B M G G 4
* * * *
300 ps Propagation Delay High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors on D, Pullup and Pulldown Resistors on D Q Output will Default LOW with Inputs Open or at VEE Pb-Free Packages are Available
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MC100LVEL16
Table 1. PIN DESCRIPTION
NC 1 8 VCC PIN D, D Q, Q VBB VCC VEE NC EP FUNCTION ECL Data Inputs ECL Data Outputs Reference Voltage Output Positive Supply Negative Supply No Connect Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open.
D
2
7
Q
D
3
6
Q
VBB
4
5
VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 75 kW > 4 KV > 400 V > 2 kV Level 1 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 79
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information.
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MC100LVEL16
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC qJA Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Wave Solder Pb Pb-Free 0 LFPM 500 LFPM Standard Board 0 LFPM 500 LFPM Standard Board 0 lfpm 500 lfpm <2 to 3 sec @ 248C <2 to 3 sec @ 260C SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 DFN8 DFN8 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 190 130 41 to 44 5% 185 140 41 to 44 5% 129 84 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100LVEL16
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 4) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current D D 0.5 -600 2215 1470 2135 1490 1.92 Min Typ 17 2295 1605 Max 23 2420 1745 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 25C Typ 17 2345 1595 Max 23 2420 1680 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 85C Typ 18 2345 1595 Max 24 2420 1680 2420 1825 2.04 Unit mA mV mV mV mV V
1.2 1.5
2.9 2.9 150
1.1 1.4
2.9 2.9 150
1.1 1.4
2.9 2.9 150
V V mA mA mA
IIH IIL
0.5 -600
0.5 -600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current D D 0.5 -600 -1085 -1830 -1165 -1810 -1.38 Min Typ 17 -1005 -1695 Max 23 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 17 -955 -1705 Max 23 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 18 -955 -1705 Max 24 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V
-2.1 -1.8
-0.4 -0.4 150
-2.2 -1.9
-0.4 -0.4 150
-2.2 -1.9
-0.4 -0.4 150
V V mA mA mA
IIH IIL
0.5 -600
0.5 -600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
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MC100LVEL16
Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= -3.3 V (Note 8)
-40C Symbol fmax tPLH tPHL tSKEW tJITTER VPP tr tf Characteristic Maximum Toggle Frequency Propagation Delay to Output Differential Single-Ended 150 100 Min Typ 1.75 275 275 5 0.7 150 120 220 1000 320 150 120 220 400 450 30 225 175 Max Min 25C Typ 1.75 300 300 5 0.7 1000 320 150 120 220 375 425 20 240 190 Max Min 85C Typ 1.75 315 315 5 0.7 1000 320 390 440 20 Max Unit GHz ps
Duty Cycle Skew (Differential) (Note 9) Random Clock Jitter (RMS) Input Swing (Note 10) Output Rise/Fall Times Q (20% - 80%)
ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary 0.3 V. 9. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 10. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100LVEL16
ORDERING INFORMATION
Device MC100LVEL16D MC100LVEL16DG MC100LVEL16DR2 MC100LVEL16DR2G MC100LVEL16DT MC100LVEL16DTG MC100LVEL16DTR2 MC100LVEL16DTR2G MC100LVEL16MNR4 MC100LVEL16MNR4G Package SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) DFN8 DFN8 (Pb-Free) Shipping 98 Units / Rail 98 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 100 Units / Rail 100 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVEL16
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC100LVEL16
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8 1
5
L
PIN 1 IDENT
4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
G DETAIL E
-W-
DIM A B C D F G K L M
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MC100LVEL16
PACKAGE DIMENSIONS
DFN8 CASE 506AA-01 ISSUE D
D A B
PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --- 0.25 0.35
E
2X
0.10 C
2X
0.10 C
0.10 C
8X
0.08 C
SEATING PLANE
A1
8X
L
K
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCCC CCCC CCCC CCCC
D2 e/2
1 8
TOP VIEW
A (A3) C e
4
SIDE VIEW
E2
5 8X
b
0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
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MC100LVEL16/D

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